Project TBD Memory Vault

DRAM Memory — Supply Chain, Manufacturing, and Unit Economics

27 min read

Deep Research Briefing: DRAM Memory — Supply Chain, Manufacturing, and Unit Economics

Prepared for: Bliss Perry and Dustin Ross, Project TBD Date: 2026-05-15

Internal Knowledge Check

Before going external, we queried the vault. Directly relevant interview material:

  • Minseok Kim (2026-05-05): Former Samsung employee with direct experience sending HBM samples. Confirmed that memory chips are closer to a commodity than logic chips and can be switched between customers. Allocation of wafers changes in real-time based on willingness to pay. Upstream suppliers don’t want customers to have visibility because it reduces pricing power. Also noted Samsung’s market cap quadrupled in one year on HBM demand dynamics.

  • Nihar (2026-05-06): Described the 3-player DRAM oligopoly (Hynix, Micron, Samsung) as the most commodity-like layer of the semiconductor stack. Flagged spot pricing on certain types and the emergence of long-term capacity reservation agreements (LTAs). Noted only ~15 bilateral relationships (3 manufacturers x 4-5 hyperscalers) cover ~80% of demand. His key reframe: “look for commodities not yet commodified rather than end chips.”

  • Jonathan (2026-05-08): The “Glencore of memory chips” conversation. Explored whether a physical commodity trading model could work for memory. Jonathan flagged that memory chips may be more commoditized than logic chips, and the session identified this as a key question requiring validation. The specific question “How commoditized are memory chips vs. logic chips, really? Is there a DRAM-like spot market already?” was left open.

This briefing directly addresses that open question from the Jonathan conversation.

1. Technical Fundamentals

How a DRAM Cell Works

A DRAM cell is among the simplest structures in all of semiconductor design: one transistor and one capacitor (called a “1T1C” cell). The capacitor stores a charge representing a binary 1 or 0. The transistor acts as a gate that allows the capacitor to be read or written.

Why “dynamic”: The capacitor’s charge leaks away over time through the transistor’s leakage current and other parasitic paths. Without intervention, data would be lost within milliseconds. A DRAM controller must periodically rewrite every cell to restore its charge — this is the “refresh” cycle, typically occurring every 32-64 milliseconds across the entire array.

Contrast with SRAM: SRAM (used in processor caches) uses 6 transistors per bit in a cross-coupled flip-flop configuration. It holds state as long as power is applied — no refresh needed. But at 6 transistors per bit vs. DRAM’s 1 transistor + 1 capacitor, SRAM is roughly 6x less dense and dramatically more expensive: approximately $5,000/GB for SRAM cache vs. $20-75/GB for DRAM.

Contrast with NAND: NAND Flash stores charge in a floating gate (or charge-trap layer) that retains data without power — it is non-volatile. NAND can be packed even more densely than DRAM (especially with 3D stacking, now at 300+ layers), but read/write operations are orders of magnitude slower.

The 1T1C architecture is what makes DRAM simultaneously useful and fragile as a product category: the extreme simplicity enables massive density and low cost-per-bit, but the need for constant refresh means DRAM consumes significant power just maintaining its state.

Manufacturing Process: DRAM vs. Logic

The differences are substantial and have direct implications for the supply chain:

Mask layers and process steps:

  • Leading-edge logic (e.g., TSMC 3nm): 80-85+ mask layers, 600-1,000+ process steps
  • DRAM (1-alpha/1-beta node): Fewer mask layers (roughly 30-40), with only 2-5 EUV exposure layers vs. 20+ EUV layers for advanced logic
  • NAND: Fewer lithography layers than DRAM at the cell level, but adds complexity through 3D vertical stacking (300+ layers)

Interconnect complexity: Logic chips require up to 10+ metal interconnect layers using copper wiring and low-k dielectrics to connect billions of heterogeneous transistors in complex routing patterns. DRAM typically needs no more than 4 metal layers, and can still use tungsten interconnects (simpler, older technology) because the wiring patterns are regular and short.

Design regularity: This is the critical structural difference. A DRAM die is essentially a massive, repeating grid of identical cells — “matrix-like arrangements of bit cells with metal wires, contacts and vias arranged in regular repeated patterns and straight lines.” This regularity allows fabrication with relaxed tolerances compared to logic, where layouts are heterogeneous and irregular, with diverse circuit blocks (ALUs, caches, I/O controllers) that each have different geometries.

What regularity means for manufacturing:

  • Yield: Defects in the regular array can often be repaired through redundant rows/columns. Logic chips have much less ability to tolerate defects in critical paths.
  • Learning curves: Because every cell is identical, process optimization feedback is faster and more statistically robust. A yield improvement applies uniformly across the die.
  • Testing: Memory testing is highly parallelized (write patterns, read patterns, compare). Logic testing requires complex test vectors tailored to the specific chip’s functionality.

DRAM process node naming: DRAM makers use a different naming convention than logic. Current nodes are labeled by generation: 1-alpha (1a), 1-beta (1b), 1-gamma (1c). These correspond roughly to feature sizes in the 12-15nm range for critical layers, but the naming does not map directly to logic node names. Samsung introduced EUV for DRAM production as early as 2020 (at the 1z generation); SK Hynix is now ramping 1c DRAM with 6 EUV layers and has installed the first High-NA EUV system (ASML EXE:5200B) at its Icheon M16 fab.

Key Technology Transitions

DDR5: The current mainstream standard (JEDEC-defined), replacing DDR4. Offers higher bandwidth (up to 6400 MT/s vs. DDR4’s 3200 MT/s) and lower voltage. DDR4 production is being phased out through 2025-2026, with capacity reallocated to DDR5, LPDDR5X, and HBM. DDR4 end-of-life is expected in 2026 for many applications.

LPDDR5X: Low-power variant used in smartphones and increasingly in AI inference. Nvidia has begun equipping AI servers with LPDDR5X (traditionally mobile memory), making Nvidia effectively “a customer with the purchasing scale of a major smartphone maker.” Lead times have stretched to 26-39 weeks as of early 2026.

HBM (High Bandwidth Memory) / HBM3E / HBM4: The transformative product. HBM stacks multiple DRAM dies vertically using through-silicon vias (TSVs), mounted on an interposer alongside a host processor. Current HBM3E stacks are 8 or 12 layers high. HBM4 (targeted for early 2026 mass production) will reach 16 layers and introduce hybrid bonding.

  • Margin: HBM commands a 5-6x price premium over equivalent DDR5 capacity. HBM3E is priced at ~$300/stack (36GB). HBM4 is expected at ~$500/stack (a ~20% premium over HBM3E).
  • Manufacturing difficulty: Yields decline with each additional stacked layer. If any die in the stack fails, the entire package is scrapped. Overall die yields remain significantly below commodity DRAM even on mature process nodes.
  • Customer base: Almost entirely AI accelerator manufacturers — Nvidia is the dominant buyer, with hyperscalers (via custom ASICs) growing. Very different from commodity DDR5 which serves PCs, phones, and generic servers.

2. Why DRAM Behaves Like a Commodity

Structural Features Driving Commodity Dynamics

This section directly addresses the open question from the Jonathan interview (2026-05-08): “How commoditized are memory chips vs. logic chips, really?”

The answer: DRAM is the closest thing to a pure commodity in the semiconductor world. Here is why:

1. Product homogeneity through JEDEC standards. JEDEC (Joint Electron Device Engineering Council) publishes open standards that define every required aspect of DRAM products — pinouts, timing specifications, voltage levels, signal protocols. The explicit goal is “eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability.” A DDR5-4800 16Gb chip from Samsung is functionally interchangeable with one from SK Hynix or Micron. There is no equivalent in logic — an Nvidia GPU and an AMD GPU are completely different products even if they serve similar functions.

2. No design differentiation. In logic, the chip designer (Apple, Nvidia, Qualcomm) creates unique intellectual property — custom architectures, instruction sets, software ecosystems. DRAM manufacturers compete almost entirely on process technology, yield, and cost. The product specifications are set by an industry consortium, not by the individual producer.

3. Low switching costs. A server OEM can qualify Samsung DDR5 and SK Hynix DDR5 on the same motherboard with minimal redesign. Qualification testing takes time, but the products are designed to be drop-in replacements. This is confirmed by Minseok Kim: “Memory chips are closer to a commodity than logic chips — they can be switched between customers. Allocation of wafers changes in real-time based on willingness to pay.”

4. Derived demand. DRAM demand is derived from end-device sales (PCs, servers, phones). Memory is a component, not a product. Buyers don’t choose a phone because of its DRAM brand — they care about capacity and speed, which are standardized. This makes DRAM demand highly cyclical and tied to broader hardware investment cycles.

5. Price transparency. DRAM has both spot markets and well-tracked contract pricing. TrendForce publishes DRAM spot prices (e.g., DDR4 8Gb and DDR5 16Gb) and contract prices quarterly. This level of price transparency is essentially absent in logic chips, where pricing is negotiated bilaterally and rarely disclosed.

The Pricing Mechanism

DRAM operates on two parallel pricing channels:

Contract pricing: Large OEMs (Dell, HP, Lenovo, hyperscalers) negotiate quarterly or monthly contract prices with Samsung, SK Hynix, and Micron directly. These prices are set through bilateral negotiation but are widely tracked by analysts (TrendForce, DRAMeXchange). In the current tight market, contract prices have been resetting mid-quarter as suppliers renegotiate upward.

Spot pricing: A liquid spot market exists, particularly through brokers and on exchanges tracked by services like DRAMeXchange. DDR5 16Gb spot prices rose from ~$6.84 to ~$27.20 in Q4 2025 — nearly a 4x increase. In some configurations, DDR4 spot prices traded above DDR5 in late 2025, inverting the traditional value hierarchy as DDR4 supply dried up.

Comparison to logic: Nvidia does not publish GPU pricing for hyperscalers. TSMC’s wafer prices are negotiated in multi-year deals with individual customers and are trade secrets. The existence of transparent, trackable DRAM pricing is itself evidence of commodity dynamics.

The DRAM Cycle

The boom-bust cycle is the defining feature of the DRAM business and has repeated for three decades:

Mechanism: Demand surges (new platform cycle, data center buildout) → prices rise → manufacturers invest heavily in new capacity → 18-24 month lag before new fabs produce output → supply overshoots demand → prices crash → manufacturers bleed losses → capex is cut → supply tightens → repeat.

Historical cycle data:

Metric2016-2018 Boom2018-2020 Bust2022-2023 Bust2025-2026 Boom
Micron peak GM58.9% (2018)——75% (2026)
Micron trough GM—30.6% (2020)~22% (2024)—
SK Hynix marginRecord Q3 2018—-28% net (2023)72% op (Q1 2026)
Revenue swing+50% YoY peak-23% YoYSevere decline+30.9% QoQ (Q3 2025)
Inventory (weeks)3-4 at peak8-10 normalBloated2-3 (SK Hynix)
DDR price moveDoubled 2017-18CrashedCrashed4x (DDR5 spot Q4 2025)

Why the cycle is more pronounced in DRAM than logic: (a) Product homogeneity means pricing is the only competitive lever; (b) capacity additions are lumpy (fabs are binary — they’re either being built or not, with 18-24 month lead times); (c) demand is derived and amplifies end-market swings; (d) there is no design-driven product cycle to create counter-cyclical demand (unlike logic, where a new GPU architecture or smartphone SoC can stimulate demand independent of the macro cycle).

Oligopoly Dynamics

Three players control ~95% of DRAM: Samsung, SK Hynix, and Micron.

Does concentration stabilize or amplify the cycle? Both, depending on the phase:

  • Stabilizing effect (current): The Big 3 have learned from past cycles. After the 2023 trough, all three were “very wary of increasing production capacity again.” Samsung and SK Hynix are reportedly cautious on expansion, and the current price rally may run past 2028 as a result. This is conscious supply discipline enabled by oligopoly structure.

  • Amplifying effect (historical): When all three do invest simultaneously (as in the mid-2010s), the synchronized capacity addition creates massive oversupply. The oligopoly coordinates on the way up (all chase the same demand signal) and the way down (all cut at once).

Nihar’s observation is directly relevant here: with only ~15 bilateral relationships (3 manufacturers x 4-5 hyperscalers) covering ~80% of demand, the market is thin enough that a formal exchange may be unnecessary — the participants can coordinate directly.

3. Manufacturing, Supply Chain, and Distribution

DRAM Fab Economics

Capex: A new DRAM fab costs approximately $15-20 billion (Micron’s new Idaho fab is ~$15B; total investment including equipment ramp is higher). For comparison, TSMC’s Fab 21 (leading-edge logic) is a ~$40B+ facility, though it is larger and more complex. Roughly 70-80% of any fab’s cost is the process equipment, not the building.

Scale: Memory fabs operate at much higher throughput than logic fabs. The “efficient scale” for a 300mm memory fab is around 120,000 wafers per month, compared to ~40,000 wpm for a leading-edge logic fab. Samsung is ramping to 200,000 1c DRAM wafers/month by late 2026 across its facilities — roughly one-third of its total DRAM output.

Build time: 19 months in Taiwan/Korea; approximately 38 months (2x) in the US due to permitting, labor costs, and construction challenges.

Current capex levels:

  • Micron: FY2026 capex raised to $20-25B (up from $13.8B in FY2025), focused on HBM capacity and 1-gamma DRAM
  • Samsung: Expanding production capacity by ~50% in 2026
  • SK Hynix: Announced plans to increase infrastructure investment by more than 4x previous announcements
  • Industry-wide: Despite the boom, TrendForce notes “memory industry to maintain cautious capex in 2026, with limited impact on bit supply growth” — the discipline narrative

Key Equipment and Bottleneck Suppliers

The bill of materials for DRAM manufacturing involves the same major equipment categories as logic, but with different intensity:

  • Lithography: ASML is the sole supplier of EUV tools. DRAM currently uses 2-6 EUV layers (vs. 20+ for advanced logic), meaning DRAM is less EUV-dependent but is increasing usage as nodes shrink. SK Hynix has installed the first High-NA EUV system for DRAM.
  • Etch and deposition: Applied Materials, Lam Research, and Tokyo Electron (TEL). TEL’s Triase CVD products hold ~40% share for titanium nitride deposition used in DRAM capacitor electrodes. These are becoming the binding constraint as resolution demands increase.
  • Metrology/inspection: KLA Corporation dominates. As features shrink, the ability to detect sub-nanometer defects becomes critical.
  • High aspect ratio (HAR) etch: Particularly important for DRAM’s tall, narrow capacitor structures and for NAND’s vertical channel holes. Lam Research has significant share here.

Geographic Concentration

DRAM manufacturing is among the most geographically concentrated industries on Earth:

Samsung fabs: Pyeongtaek (P1-P4, P5 under construction) and Hwaseong, South Korea; Xi’an, China. Samsung announced a new fab in Taylor, Texas (US) but has faced delays.

SK Hynix fabs: Icheon (M14, M16) and Cheongju (M15, M15X under construction), South Korea; Wuxi, Chongqing, and Dalian, China. SK Hynix is building its first US advanced packaging plant in Indiana ($3.9B investment).

Micron fabs: Hiroshima, Japan (main HBM front-end); Taichung and Linkou, Taiwan (expanding with former AU Optronics facilities); Boise, Idaho, USA (new fab, first wafer output mid-2026); New York (planned); Singapore ($7B HBM fab investment).

Geopolitical implications: South Korea alone accounts for the vast majority of global DRAM production (Samsung + SK Hynix = ~65-70% of revenue). Both companies have significant operations in China, which creates tension with US export controls. A disruption on the Korean peninsula would be catastrophic for the global memory supply. Micron’s geographic diversification (Japan, Taiwan, Singapore, US) is a strategic differentiator but comes at higher cost.

A striking data point: OpenAI’s Stargate project has signed agreements with Samsung and SK Hynix for up to 900,000 DRAM wafers/month — potentially ~40% of total global DRAM output — with deliveries locked through 2029. The deal could be worth over $70 billion.

Assembly, Packaging, and Test

Standard DRAM: After wafer fabrication, individual dies are singulated, tested, and packaged onto modules (DIMMs, SO-DIMMs). This is relatively straightforward packaging — wire bonding, encapsulation, and PCB mounting. It can be done by the manufacturer or outsourced to OSATs (ASE, Amkor, JCET). Module makers like Kingston and Corsair buy tested DRAM chips and assemble them onto their own module PCBs.

HBM changes everything: HBM requires advanced 2.5D packaging that is fundamentally different:

  • Individual DRAM dies are thinned to ~30-40 micrometers
  • Through-silicon vias (TSVs) are drilled through each die
  • Dies are stacked 8-16 high using micro-bumps or hybrid bonding
  • The stack is mounted on a silicon interposer alongside the host processor (GPU/ASIC) using TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) process or equivalent
  • This interposer connects thousands of signal paths between the HBM stack and the logic die

CoWoS as bottleneck: TSMC’s CoWoS advanced packaging capacity has been the single tightest constraint in the AI semiconductor stack, “oversubscribed through at least 2026.” SK Hynix performs its own HBM stacking (using its MR-MUF process) but still depends on TSMC for the final interposer integration with the host GPU. This creates a complex dependency chain.

HBM4 introduces further complexity: HBM4 must be physically bonded to the logic die during the packaging process, requiring perfect coordination between the memory manufacturer’s production cycle and TSMC’s packaging schedule.

Distribution and Route to Market

This is where DRAM’s commodity nature shows most clearly in the value chain:

Tier 1: Direct sales to large OEMs and hyperscalers. Samsung, SK Hynix, and Micron sell directly to major buyers — hyperscalers (AWS, Google, Meta, Microsoft), server OEMs (Dell, HPE, Lenovo), PC OEMs (Dell, HP, Lenovo), and smartphone makers (Apple, Samsung Mobile). This is bilateral negotiation on contract pricing. For HBM specifically, sales are almost entirely direct and allocation-based — there is no distribution channel for HBM.

Tier 2: Module makers. Companies like Kingston Technology (which commands ~68% of the third-party DRAM module market) and Corsair buy bare DRAM chips from the Big 3 and assemble them onto finished modules. Kingston serves OEMs, data center operators, and the retail aftermarket through distributors. This is a value-added step but a thin-margin one — Kingston competes primarily on reliability testing, locked BOMs (bill of materials consistency), and distribution reach.

Tier 3: Franchised distributors. Arrow, Avnet, DigiKey, Mouser distribute DRAM modules (mostly Kingston/Corsair branded, some Samsung/Micron branded) to mid-market and smaller OEMs. In the current shortage, authorized distributors are critical for authentication and traceability — counterfeit risk rises sharply during supply crunches.

Contrast with logic distribution:

  • Analog/mixed-signal (TI, NXP): Heavy reliance on distribution. NXP’s distributors (Arrow, Avnet) account for ~55% of revenue. These markets have thousands of SKUs serving fragmented customer bases. Texas Instruments has been moving toward direct sales, but distribution remains central for the long tail.

  • High-end logic (Nvidia, AMD GPUs): Nvidia’s data center business (78% of revenue) is almost entirely direct-to-hyperscaler. Nvidia’s sales teams manage multi-billion-dollar, multi-year contracts with AWS, Microsoft, Google, Oracle, and Meta. There is no distributor between Nvidia and its largest customers. Consumer GPUs flow through add-in-board partners and retail, but the highest-value business bypasses distribution entirely.

  • DRAM sits in between: More direct than analog (because the customer base is more concentrated) but less direct than Nvidia’s GPU business (because DRAM is fungible and doesn’t require the same solution-selling relationship). The module-maker layer (Kingston, Corsair) has no real equivalent in the logic world.

4. Unit Economics and Market Structure

Cost Structures: Commodity DDR5 vs. HBM3E

Commodity DDR5 (approximate):

  • Wafer cost: ~$2,500-4,000 per 300mm wafer (depending on node and EUV usage)
  • Dies per wafer: Several hundred (for a 16Gb die)
  • Yield: 85-95% for mature commodity DRAM
  • Packaging: Standard wire-bond packaging, relatively inexpensive
  • Test: Highly parallelized, low per-unit cost
  • Effective cost per GB: Low single dollars at the die level

HBM3E (approximate):

  • Same underlying wafer cost for the DRAM dies
  • But: each GB of HBM consumes roughly 3x the wafer capacity of DDR5 due to larger dies, lower yields from stacking, and die binning requirements
  • TSV processing, wafer thinning, and stacking add significant cost per die
  • CoWoS/interposer packaging: ~$70+ per unit for standard configurations
  • Test: More complex; the entire stack must be tested as a unit, and a single failed die scraps the stack
  • End result: HBM costs $8-10/GB vs. DDR5 at roughly $1.50-3/GB — approximately 3-5x premium
  • HBM3E sells at ~$300 per 36GB stack
  • In an Nvidia H100 SXM5: HBM3 cost is ~$1,350 (six stacks, 80GB), representing ~40% of the ~$3,320 estimated manufacturing cost

Margins Across the Cycle

The margin range in DRAM is extreme — among the widest of any major industry:

Trough (2022-2023):

  • SK Hynix: -28% net margin (full year 2023)
  • Micron: ~22% gross margin (FY2024)
  • Samsung semiconductor division: ~0.27 trillion KRW operating profit in Q4 2022 (near zero)

Peak (current, Q4 2025 - Q1 2026):

  • SK Hynix: 72% operating margin (Q1 2026)
  • Micron: 75% gross margin record, 56% gross margin in fiscal Q1 2026 (climbing to projected 67% in Q2)
  • Samsung memory: Operating margin exceeding 70% in Q1 2026; Q1 2026 operating profit (53.7 trillion KRW) exceeded the company’s entire FY2025 operating profit
  • TrendForce projected Samsung and SK Hynix gross margins would surpass TSMC’s in Q4 2025

That last point deserves emphasis: Memory makers — traditionally price-takers in a commodity market — briefly surpassed TSMC’s gross margins. TSMC’s gross margin was 62.3% in Q4 FY2025. This is extraordinary and reflects the current supply-demand imbalance.

Projected downturn profile (if cycle persists): Analysts project shallower corrections this cycle: 15-25% revenue declines with margins compressing to the 35-40% range, contrasting the historical 30-40% revenue drops and sub-25% margin troughs. The reasoning is that sustained AI demand creates a higher floor. Whether this structural break thesis holds is unproven.

Does HBM Escape Commodity Dynamics?

Arguments for durable differentiation:

  • TSV layout and design is proprietary — a genuine area of technical differentiation between manufacturers
  • Yields are persistently lower than commodity DRAM, limiting supply expansion
  • Qualification cycles are long and customer-specific (Nvidia must validate each supplier’s HBM)
  • Advanced packaging capacity (CoWoS) is structurally constrained
  • Long-term agreements (LTAs) through 2026-2029 reduce spot market exposure
  • Manufacturing complexity increases with each generation (HBM3E 12-high, HBM4 16-high)

Arguments for eventual commoditization:

  • All three manufacturers are converging on similar technology (all making HBM3E, all ramping HBM4)
  • JEDEC is standardizing HBM specifications, as it did with DDR
  • The price premium has already narrowed from ~10x over commodity DRAM to ~4-6x
  • If/when CoWoS capacity loosens, the packaging bottleneck that supports pricing power eases
  • SK Hynix internally modeled potential HBM oversupply risk by 2027 and quietly cut HBM-specific capex in 2025

Assessment: HBM is currently in a sweet spot of structural scarcity and technical differentiation. It behaves more like a specialty chemical than a commodity today. But the forces of commoditization — standardization, multi-sourcing, capacity buildout — are in motion. The question is timing: 2-3 years of elevated margins seems likely, but a 10-year moat would be surprising. Samsung’s aggressive capacity expansion (targeting 30%+ HBM market share from 17%) could accelerate convergence.

Competitive Positions of the Big 3

SK Hynix: Current market leader in both DRAM (34% revenue share, Q3 2025) and HBM (62% share, Q2 2025). First to install High-NA EUV for DRAM. Deepest relationship with Nvidia. Has sold out entire 2026 HBM and DRAM supply. Strength: technology leadership, yield maturity, Nvidia relationship. Weakness: concentrated in South Korea (geopolitical risk), less diversified manufacturing base.

Samsung: Historically dominant, now #2 in DRAM (33% revenue share) and distant #3 in HBM (17% share). Stumbled on HBM3E yields and Nvidia qualification, but aggressively ramping 1c DRAM (200K wafers/month target by late 2026). The only vertically integrated player (fab + foundry + packaging + end products). Plans to lift HBM share above 30%. Strength: massive scale, vertical integration, captive demand from Samsung Electronics devices. Weakness: execution issues on HBM qualification, organizational bureaucracy.

Micron: #3 in DRAM (26% share) but #2 in HBM (21% share, having overtaken Samsung). Only US-based DRAM manufacturer. Most geographically diversified fab footprint (Japan, Taiwan, Singapore, US). FY2026 capex of $20-25B. Signed first 5-year customer deal. Strength: geographic diversification, US government support (CHIPS Act), HBM execution. Weakness: smallest scale, highest cost structure in DRAM historically.

5. Contrast with Logic and NAND

Structural Comparison Table

DimensionDRAMLogic (Foundry/Fabless)NAND Flash
Design complexityLow (repeating array)Very high (heterogeneous)Medium (repeating array, but 3D stacking)
Mask layers~30-4050-85+Fewer per layer, but 300+ physical layers
Process stepsFewer, more regular600-1,000+Fewer litho steps, but extreme etch/deposition
Product differentiationMinimal (JEDEC standards)Extreme (custom designs)Low-moderate (capacity/speed grades)
Pricing dynamicsTransparent, spot + contractOpaque, bilateralSemi-transparent, spot exists
Market concentration3 players, ~95%TSMC alone ~72% foundry; but thousands of fabless designers5-6 players (Samsung 32%, SK Hynix 19%, Kioxia 15%, Micron, WD/SanDisk)
Customer switching costsLow (standardized)Very high (IP, EDA tools, process tuning)Low-moderate
Margin profileExtreme cyclicality (-28% to 72% op margin)Steady, premium (TSMC ~60%+ GM)Cyclical, somewhat less extreme than DRAM
Capex intensityVery highVery high (higher per fab)Very high

Why TSMC Can Charge Premium Margins

TSMC’s structural advantage comes from the nature of logic chip design:

Design-driven differentiation: Every chip that TSMC manufactures is a unique, custom design owned by the customer (Apple, Nvidia, AMD, Qualcomm). The customer’s IP — worth billions in R&D — is locked into TSMC’s process technology. Switching to another foundry (Samsung Foundry, Intel) requires re-designing, re-characterizing, and re-qualifying the chip. This process takes 12-24+ months and costs hundreds of millions of dollars.

Technology monopoly: For leading-edge nodes (3nm and below), TSMC holds over 90% market share. It is the only foundry capable of manufacturing the most advanced chips at scale with competitive yields. Intel’s yields are estimated at 65-75% at comparable nodes, 5-15 percentage points below TSMC.

Value-based pricing: TSMC has transitioned from cost-plus pricing to value-based pricing. A chip manufactured on TSMC’s N3 process enables products worth billions to the end customer. TSMC captures a share of that value, not just the manufacturing cost. Wafer prices have increased 15%+ per year since 2019, and gross margins have increased 3.3x in 2025 alone.

None of this applies to DRAM. DRAM products are standardized, interchangeable, and not design-differentiated. The DRAM manufacturer cannot charge value-based pricing because the customer’s switching cost is near zero. The product is the same regardless of who makes it.

NAND’s Position on the Commodity Spectrum

NAND sits between DRAM and logic, but closer to DRAM:

More players: NAND has 5-6 meaningful competitors (Samsung 32%, SK Hynix 19%, Kioxia 15%, SanDisk 12%, Micron ~12%). More competitors means less ability to coordinate on supply discipline.

Different scaling path: NAND scales by adding vertical layers (now 300-400+), not by shrinking the horizontal feature size. This means NAND is less dependent on EUV lithography but more dependent on high-aspect-ratio etch and deposition — different equipment bottlenecks.

Different demand drivers: NAND serves storage (SSDs, USB drives, smartphones) rather than memory. AI-driven demand is growing (enterprise SSDs for data center storage) but less directly than DRAM/HBM which sits directly in the compute path.

NAND cycle: Also cyclical, but historically less extreme in margin swings than DRAM. The additional competitors and different demand drivers create somewhat more muted booms and busts, though the current cycle is affecting both: NAND prices climbed 246% from start of 2025 through December.

Market Size Context

The global DRAM market is approximately $121-131 billion in annual revenue (2024-2025 estimates vary by source), with HBM projected to grow from $38B (2025) to $54-58B (2026) as a segment within that. The total memory market (DRAM + NAND) exceeded $190B in 2025.

Surprises and Non-Obvious Insights

1. Memory makers are currently earning higher margins than TSMC

TrendForce projected that Samsung and SK Hynix would push memory gross margins above TSMC’s in Q4 2025. SK Hynix posted a 72% operating margin in Q1 2026. This is counterintuitive: the textbook story is that commodity producers are price-takers with thin margins, while differentiated monopolists like TSMC earn fat margins. The current inversion is driven by the extreme supply-demand imbalance for HBM and the deliberate capacity discipline of the oligopoly after 2023’s devastating trough. The non-obvious point: even in commodity markets, a tight enough oligopoly with aligned incentives and a demand shock can temporarily achieve monopoly-like economics. The question is how long the discipline holds.

2. AI is cannibalizing your laptop’s RAM — literally, from the same wafer

Each gigabyte of HBM consumes approximately 3x the wafer capacity of standard DDR5. As Samsung, SK Hynix, and Micron aggressively convert wafer capacity from commodity DDR to high-margin HBM, they are physically reducing the supply of ordinary RAM. DDR5 spot prices quadrupled in Q4 2025. DDR4 prices in some configurations traded above DDR5 — an inversion that makes no technical sense but reflects the supply reality: manufacturers are choosing not to make DDR4 because HBM and DDR5 are more profitable per wafer. The non-obvious point: AI’s hunger for HBM is imposing a direct cost on every PC, phone, and non-AI server buyer in the world. This is not a “separate market” — it is the same fabs, the same wafers, the same capacity.

3. The entire DRAM market runs on roughly 15 bilateral relationships

Nihar identified that 3 manufacturers x 4-5 hyperscalers cover ~80% of DRAM demand, yielding only ~15 bilateral relationships. This is confirmed by the Stargate deal: OpenAI alone has signed for up to 900,000 DRAM wafers/month from Samsung and SK Hynix, potentially representing ~40% of total global DRAM output through 2029. The non-obvious point: what looks like a “market” of billions of devices is actually mediated by an absurdly thin network of bilateral agreements between a handful of entities. There is no real “market” in the economic sense — no price discovery mechanism, no exchange, no transparent order book. It is a series of private negotiations between 3 producers and a small number of very large buyers.

Convergences with Internal Sources

  • Minseok’s claim that memory chips can be switched between customers and that allocation changes in real-time is fully confirmed by public evidence of spot markets, mid-quarter contract repricing, and JEDEC standardization.
  • Nihar’s identification of memory as the most commodity-like layer is confirmed by every structural analysis.
  • Jonathan’s Glencore analogy gains substance: DRAM has spot pricing, contract pricing, inventory dynamics, supply concentration, and demand volatility that resemble physical commodities.

Divergences

  • Minseok stated Samsung’s market cap quadrupled on HBM demand. Public data shows Samsung’s stock has risen substantially but the “quadrupled” figure may be an overstatement or refers to a specific time window. Samsung’s semiconductor earnings did grow dramatically (Q1 2026 operating profit exceeded all of FY2025), but the company-level market cap increase has been more moderate given Samsung’s diversified business. Flagged for verification.

Open Questions

  1. What does the actual HBM procurement workflow look like inside a hyperscaler? How far in advance are LTAs negotiated? Who owns the relationship — procurement, chip engineering, or infrastructure planning? (Could be answered by: someone at Google/AWS/Meta in infrastructure procurement)

  2. Is the current supply discipline truly structural, or will it break? Samsung’s aggressive expansion plans (50% capacity increase in 2026) could be the catalyst. SK Hynix quietly cutting HBM capex on oversupply risk modeling suggests internal concern. (Could be answered by: industry analysts at TrendForce or SemiAnalysis, or equity analysts covering the Big 3)

  3. What happens to DRAM pricing if/when AI inference demand plateaus? The “supercycle” thesis assumes demand is elastic to lower prices (like energy), but this is unproven. (Could be answered by: data center capacity planners, cloud infrastructure economists)

  4. How real is the counterfeit risk in DRAM distribution during shortages? Findchips emphasizes authorized sourcing, but what does enforcement actually look like? (Could be answered by: CBP enforcement contacts, authorized distributor compliance teams)

Confidence Summary

  • Technical fundamentals: High confidence. Well-documented in public sources and academic materials.
  • Market structure and share figures: High confidence for recent quarters. Specific figures from TrendForce and Counterpoint Research are industry-standard.
  • Margin figures: High confidence for recent data. Historical ranges are approximate but directionally solid.
  • HBM cost structure: Medium confidence. Specific per-GB figures ($8-10/GB) are estimates that vary by source. The 3x wafer consumption figure is well-sourced.
  • Cycle projection (shallower future downturns): Low confidence. This is the consensus view among bulls but is fundamentally unproven and contradicts 30 years of history.
  • Distribution channel details: Medium confidence. The broad structure is clear but specific revenue splits between direct/distributor/module-maker channels are not publicly disclosed by the Big 3.

Sources Consulted

  • TrendForce DRAM market data and pricing reports (Q4 2025, Q1 2026)
  • Counterpoint Research Global DRAM and HBM Market Share
  • Tom’s Hardware — HBM eating your RAM; SK Hynix US packaging plant; OpenAI Stargate DRAM deal; TSMC wafer price increases; US fab build costs
  • UncoverAlpha — DRAM cycle analysis
  • Dr. Robert Castellano — HBM pricing analysis; SK Hynix dethrones Samsung
  • IEEE Spectrum — DRAM Moore’s Law / AI shortage
  • Entegris Blog — DRAM device fabrication
  • Micron Blog — Inside 1-Alpha DRAM
  • FusionWW — CoWoS and HBM bottleneck
  • Construction Physics — How to build a $20B fab
  • Asianometry — Economics of TSMC Giga-Fabs
  • Kingston Technology — Company and market position
  • JEDEC — Standards and specifications
  • Wikipedia — DRAM, JEDEC memory standards
  • Diffen — SRAM vs DRAM
  • Findchips — 2026 DRAM buyer playbook
  • Semiconductor Engineering — Fab cycle times
  • SemiWiki — 1c DRAM investment
  • TweakTown — SK Hynix 1c DRAM 6 EUV layers
  • DigiTimes — Micron FY26 capex
  • DataCenterDynamics — Samsung SK Hynix 2026 capacity expansion
  • CNBC — Samsung Q1 2026 earnings

Graph View